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Preliminary Technical Data
FEATURES
Low Power, 24-Bit Sigma-Delta ADC with InAmp and Embedded Reference (6 Channel) AD7794
APPLICATIONS
Temperature measurement Pressure measurement Weigh scales
Six Differential Analog Inputs Low Noise Programmable Gain Instrumentation-Amp RMS noise: 80 nV (Gain = 64) Bandgap Reference with 5 ppm/ C Drift typ Power Supply: 2.7 V to 5.25 V operation Normal: 400 A typ Power-down: 1 A max Update Rate: 4 Hz to 500 Hz Simultaneous 50 Hz/60 Hz Rejection Internal Clock Oscillator Reference Detect Programmable Current Sources (10 A/200 A/1 mA) On-Chip Bias Voltage Generator 100 nA Burnout Currents Low Side Power Switch Independent Interface Power Supply 24-Lead TSSOP Package
GENERAL DESCRIPTION
The AD7794 is a low power, complete analog front end for low frequency measurement applications. It contains a low noise 24-bit - ADC with six differential inputs. The on-chip low noise instrumentation amplifier means that signals of small amplitude can be interfaced directly to the ADC. The device contains a precision low noise, low drift internal reference for absolute measurements. An external reference can also be used if ratiometric measurements are required. Other on-chip features include programmable excitation current sources and a bias voltage generator for temperature applications along with 100 nA burnout currents. For pressure and weighscale applications, a low-side power switch is available to power down the bridge between conversions to minimize the power consumption of the system. The device can be operated with the internal clock or, alternatively, an external clock can be used if synchronizing several devices. The output data rate from the part is software programmable and can be varied from 4 Hz to 500 Hz. The part operates with a power supply from 2.7 V to 5.25 V. It consumes a current of 450 uA maximum and is housed in a 24lead TSSOP package.
INTERFACE
3-wire serial SPI(R), QSPITM, MICROWIRETM, and DSP compatible Schmitt trigger on SCLK
FUNCTIONAL BLOCK DIAGRAM
GND VBIAS AIN1(+) AIN1(-) AIN2(+) AIN2(-) AIN3(+) AIN3(-) AIN5(+)/IOUT2 AIN5(-)/IOUT1 AIN6(+)/P1 AIN6(-)/P2 PSW GND CLK VDD BANDGAP REFERENCE GND IN-AMP MUX SIGMA DELTA ADC SERIAL INTERFACE AND CONTROL LOGIC DOUT/RDY DIN SCLK CS REFERENCE DETECT AVDD AIN4(+)/REFIN2(+) REFIN1(+) AIN4(-)/REFIN2(-) REFIN1(-)
GND VDD TEMP SENSOR INTERNAL CLOCK
AD7794
DVDD
REV.PrE
6/04.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD7794 TABLE OF CONTENTS
AD7794--Specifications.................................................................. 3 Timing Characteristics, .................................................................... 9 Absolute Maximum Ratings.......................................................... 11 ESD Caution................................................................................ 11 Pin Configuration and Function Descriptions........................... 12 Typical Performance Characteristics ........................................... 14 On-chip Registers ........................................................................... 15 Communications Register (RS2, RS1, RS0 = 0, 0, 0) .............. 15 Status Register (RS2, RS1, RS0 = 0, 0, 0; Power-on/Reset = 0x88)............................................................................................. 16 Mode Register (RS2, RS1, RS0 = 0, 0, 1; Power-on/Reset = 0x000A)........................................................................................ 16 Configuration Register (rs2, RS1, RS0 = 0, 1, 0; Poweron/Reset = 0x0710) .................................................................... 18 Data Register (RS2, RS1, RS0 = 0, 1, 1; Power-on/Reset = 0x000000) .................................................................................... 20 ID Register (RS2, RS1, RS0 = 1, 0, 0; Power-on/Reset = 0xxF) ....................................................................................................... 20 IO Register (RS2, RS1, RS0 = 1, 0, 1; Power-on/Reset = 0x00) ....................................................................................................... 20 OFFSET Register (RS2, RS1, RS0 = 1, 1, 0; Power-on/Reset = 0x800000) .................................................................................... 21
Preliminary Technical Data
FULL-SCALE Register (RS2, RS1, RS0 = 1, 1, 1; Poweron/Reset = 0x5xxxx5) ................................................................ 21 ADC Circuit Information.............................................................. 22 Overview ..................................................................................... 22 Noise Performance ..................................................................... 22 Digital Interface .......................................................................... 23 Single Conversion Mode ....................................................... 24 Continuous Conversion Mode............................................. 24 Continuous Read Mode ........................................................ 25 Circuit Description......................................................................... 26 Analog Input Channel ............................................................... 26 Bipolar/Unipolar Configuration .............................................. 26 Data Output Coding .................................................................. 26 Reference ..................................................................................... 26 VDD Monitor ................................................................................ 27 Grounding and Layout .............................................................. 27 Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 29
REVISION HISTORY
REV.PrE, June 2004: Initial Version
REV.PrE 6/04 | Page 2
Preliminary Technical Data AD7794--SPECIFICATIONS1
AD7794
Table 1. (AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.)
Parameter AD7794 (CHOP ENABLED) Output Update Rate No Missing Codes2 Resolution (pk - pk) Output Noise and Update Rates Integral Nonlinearity Offset Error3 Offset Error Drift vs. Temperature4 Full-Scale Error3, 5 Gain Drift vs. Temperature4 Power Supply Rejection ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Unbuffered Mode Buffered Mode In-Amp Enabled Common Mode Voltage Analog Input Current Buffered Mode or In-Amp Enabled Average Input Current2 Average Input Current Drift Unbuffered Mode Average Input Current Average Input Current Drift Normal Mode Rejection2 Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz Common Mode Rejection @DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 AD7794B 4 500 24 16 19 See Tables in ADC Description 15 25 3 10 10 0.5 3 90 REFIN/Gain Unit Hz min nom Hz max nom Bits min Bits p-p Bits p-p Test Conditions/Comments Settling Time = 2/Output Update Rate fADC 125 Hz Gain = 128, 16.6 Hz Update Rate, VREF = 2.5 V Gain = 1, 16.6 Hz Update Rate, VREF = 2.5 V
ppm of FSR max ppm of FSR max V typ nV/C typ V typ ppm/C typ ppm/C typ dB min V nom
3.5 ppm typ. Gain = 1 to 32 5 ppm typ, Gain = 64 or 128
Gain = 1 or 2 Gain = 4 to 128 100 dB typ, AIN = FS/2 REFIN = REFIN(+) - REFIN(-) or Internal Reference, Gain = 1 to 128 Gain = 1 or 2 Gain = 1 or 2 Gain = 4 to 128 Gain = 4 to 128
GND - 30 mV AVDD + 30 mV GND + 100 mV AVDD - 100 mV GND + 300 mV AVDD - 1.1 0.5
V min V max V min V max V min V max V min
200 2 400 50 1
pA max pA/C typ nA/V typ pA/V/C typ nA max Gain = 1 or 2 Input current varies with input voltage. AIN6(+) / AIN6(-)
70 84 90 80 94 90 90 100 100
dB min dB min dB min dB min dB min dB min dB min dB min dB min
80 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 10106 90 dB typ, 50 1 Hz, FS[3:0] = 10016 100 dB typ, 60 1 Hz, FS[3:0] = 10006 90 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 10106 100 dB typ, 50 1 Hz, FS[3:0] = 10016 100 dB typ, 60 1 Hz, FS[3:0] = 10006 AIN = +FS/2 FS[3:0] = 10106 50 1 Hz, 60 1 Hz, FS[3:0] = 10106 50 1 Hz (FS[3:0] = 10016), 60 1 Hz (FS[3:0] = 10006)
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AD7794
Parameter REFERENCE INPUT Internal Reference Initial Accuracy Internal Reference Drift Internal Reference Noise External REFIN Voltage Reference Voltage Range2 Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift Normal Mode Rejection2 Common Mode Rejection Reference Detect Levels AD7794B 1.17 0.01% 5 15 2 2.5 0.1 AVDD GND - 30 mV AVDD + 30 mV 400 0.03 Same as for Analog Inputs Same as for Analog Inputs 0.3 0.65 Unit V min/max ppm/C typ ppm/C max V RMS V nom V min V max V min V max nA/V typ nA/V/C typ
Preliminary Technical Data
Test Conditions/Comments
Gain = 1, Update Rate = 16.6 Hz. Includes ADC Noise. REFIN = REFIN(+) - REFIN(-)
V min V max
NOXREF Bit Inactive if VREF < 0.3 V NOXREF Bit Active if VREF > 0.65 V
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Preliminary Technical Data
Parameter AD7794 (CHOP DISABLED) Output Update Rate No Missing Codes2 Resolution Output Noise and Update Rates Integral Nonlinearity Offset Error3 Offset Error Drift vs. Temperature4 Full-Scale Error3, 5 Gain Drift vs. Temperature4 Power Supply Rejection ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Unbuffered Mode Buffered Mode In-Amp Enabled Common Mode Voltage Analog Input Current Buffered Mode or In-Amp Enabled Average Input Current2 Average Input Current Drift Unbuffered Mode Average Input Current Average Input Current Drift Normal Mode Rejection2 Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz Common Mode Rejection @DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 REFERENCE INPUT Internal Reference Initial Accuracy Internal Reference Drift AD7794B 4 500 24 15.5 18.5 See Tables in ADC Description 15 25 200/Gain 200/Gain 10 0.5 3 80 REFIN/Gain Unit Hz min nom Hz max nom Bits min Bits p-p Bits p-p Test Conditions/Comments Settling Time = 1/Output Update Rate
AD7794
fADC 125 Hz Gain = 128, 16.6 Hz Update Rate, VREF = 2.5 V Gain = 1, 16.6 Hz Update Rate, VREF = 2.5 V
ppm of FSR max ppm of FSR max V typ nV/C typ V typ ppm/C typ ppm/C typ dB min V nom
3.5 ppm of FSR typ. Gain = 1 to 32 5 ppm of FSR typ, Gain = 64 or 128 Without Calibration
Gain = 1 or 2 Gain = 4 to 128 100 dB typ, AIN = FS/2 REFIN = REFIN(+) - REFIN(-) or Internal Reference, Gain = 1 to 128 Gain = 1 or 2 Gain = 1 or 2 Gain = 4 to 128 Gain = 4 to 128
GND - 30 mV AVDD + 30 mV GND + 100 mV AVDD - 100 mV GND + 100 mV AVDD - 1.1 0.5
V min V max V min V max V min V max V min
200 2 400 50 1
pA max pA/C typ nA/V typ pA/V/C typ nA max Gain = 1 or 2 Input current varies with input voltage. AIN6(+) / AIN6(-)
60 80 90 60 94 90 80 80 80
dB min dB min dB min dB min dB min dB min dB min dB min dB min
70 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 10106 90 dB typ, 50 1 Hz, FS[3:0] = 10016 100 dB typ, 60 1 Hz, FS[3:0] = 10006 70 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 10106 100 dB typ, 50 1 Hz, FS[3:0] = 10016 100 dB typ, 60 1 Hz, FS[3:0] = 10006 AIN = +FS/2 FS[3:0] = 10106 50 1 Hz, 60 1 Hz, FS[3:0] = 10106 50 1 Hz (FS[3:0] = 10016), 60 1 Hz (FS[3:0] = 10006)
1.17 0.01% 5 15
V min/max ppm/C typ ppm/C max
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AD7794
Parameter Internal Reference Noise External REFIN Voltage Reference Voltage Range2 Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift Normal Mode Rejection2 Common Mode Rejection Reference Detect Levels AD7794B 2 2.5 0.1 V DD GND - 30 mV AVDD + 30 mV 400 0.03 Same as for Analog Inputs Same as for Analog Inputs 0.3 0.65 Unit V RMS V nom V min V max V min V max nA/V typ nA/V/C typ
Preliminary Technical Data
Test Conditions/Comments Gain = 1, Update Rate = 16.6 Hz. Includes ADC Noise. REFIN = REFIN(+) - REFIN(-)
V min V max
NOXREF Bit Inactive if VREF < 0.3 V NOXREF Bit Active if VREF > 0.65 V
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Preliminary Technical Data
Parameter AD7794B EXCITATION CURRENT SOURCES (IEXC1 and IEXC2) Output Current 10/200/1000 Initial Tolerance at 25C 5 Drift 200 Initial Current Matching at 25C 1 Drift Matching 20 Line Regulation (VDD) 2.1 Load Regulation 0.3 Output Compliance AVDD - 0.6 AVDD - 1 GND - 30 mV BIAS VOLTAGE GENERATOR VBIAS AVDD/2 VBIAS Generator Start-Up Time TBD TEMPERATURE SENSOR Accuracy TBD LOW SIDE POWER SWITCH RON 5 7 Allowable Current 20 DIGITAL OUTPUTS (P1 & P2) VOH, Output High Voltage2 AVDD - 0.6 VOL, Output Low Voltage2 0.4 VOH, Output High Voltage2 4 VOL, Output Low Voltage2 0.4 Floating-State Leakage Current 1 Floating-State Output Capacitance 10 INTERNAL/EXTERNAL CLOCK Internal Clock Fequency Duty Cycle Drift External Clock Frequency Duty Cycle LOGIC INPUTS All Inputs Except SCLK, DIN and CLK2 VINL, Input Low Voltage VINH, Input High Voltage SCLK and DIN (Schmitt-Triggered Input)2 VT(+) VT(-) VT(+) - VT(-) VT(+) VT(-) VT(+) - VT(-) CLK2 VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage 64 2% 50:50 0.01 64 45:55 Unit A nom % typ ppm/C typ % typ ppm/C typ ppm/V max ppm/V typ V max V max V min V nom ms/nF typ C typ max max mA max V min V max V min V max A max pF typ AVDD = 5 V AVDD = 3 V Continuous Current AVDD = 3 V, ISOURCE = 100 A AVDD = 3 V, ISINK = 100 A AVDD = 5 V, ISOURCE = 200 A AVDD = 5 V, ISINK = 800 A Test Conditions/Comments
AD7794
Matching between IEXC1 and EXC2. VOUT = 0 V AVDD = 5 V 5%. Typically 1.25 ppm/V Current Sources Programmed to 10 A or 200 A Current Sources Programmed to 1 mA
Dependent on the Capacitance connected to AIN
64 2% 50:50 0.01 64 45:55
0.8 0.4 2.0
V max V max V min
DVDD = 5 V DVDD = 3 V DVDD = 3 V or 5 V
1.4/2 0.8/1.4 0.3/0.85 0.9/2 0.4/1.1 0.3/0.85 0.8 0.4 3.5
V min/V max V min/V max V min/V max V min/V max V min/V max V min/V max V max V max V min
REV.PrE 6/04 | Page 7
DVDD = 5 V DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 3 V DVDD = 5 V DVDD = 3 V DVDD = 5 V
AD7794
Parameter VINH, Input High Voltage Input Currents Input Capacitance LOGIC OUTPUTS (Including CLK) VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2 VOL, Output Low Voltage2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS7 Power Supply Voltage AVDD - GND DVDD - GND Power Supply Currents IDD Current AD7794B 2.5 1 10 DVDD - 0.6 0.4 4 0.4 1 10 Offset Binary 1.05 x FS -1.05 x FS 0.8 x FS 2.1 x FS Unit V min A max pF typ V min V max V min V max A max pF typ V max V max V min V min V min
Preliminary Technical Data
Test Conditions/Comments DVDD = 3 V VIN = DVDD or GND All Digital Inputs DVDD = 3 V, ISOURCE = 100 A DVDD = 3 V, ISINK = 100 A DVDD = 5 V, ISOURCE = 200 A DVDD = 5 V, ISINK = 1.6 mA (DOUT/RDY)/800 A (CLK)
2.7/5.25 2.7/5.25 150 175 380 450 1
V min/max V min/max A max A max A max A max A max 125 A typ, Unbuffered Mode, Ext. Reference 150 A typ, Buffered Mode, In-Amp Bypassed, Ext Ref 330 A typ, In-Amp used, Ext. Ref 400 A typ, In-Amp used, Int Ref
IDD (Power-Down Mode)
1 2 3
Temperature Range -40C to +105C. Specification is not production tested but is supported by characterization data at initial product release. Following a self-calibration, this error will be in the order of the noise for the programmed gain and update rate selected. A system calibration will completely remove this error. 4 Recalibration at any temperature will remove these errors. 5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V). 6 FS[3:0] are the four bits used in the mode register to select the output word rate. 7 Digital inputs equal to DVDD or GND.
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Preliminary Technical Data TIMING CHARACTERISTICS8, 9
AD7794
Table 2. (AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.)
Parameter t3 t4 Read Operation t1 Limit at TMIN, TMAX (B Version) 100 100 0 60 80 0 60 80 10 80 100 10 0 30 25 0 Unit ns min ns min ns min ns max ns max ns min ns max ns max ns min ns max ns max ns min ns min ns min ns min ns min Conditions/Comments SCLK High Pulsewidth SCLK Low Pulsewidth CS Falling Edge to DOUT/RDY Active Time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK Active Edge to Data Valid Delay11 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus Relinquish Time after CS Inactive Edge SCLK Inactive Edge to CS Inactive Edge SCLK Inactive Edge to DOUT/RDY High CS Falling Edge to SCLK Active Edge Setup Time11 Data Valid to SCLK Edge Setup Time Data Valid to SCLK Edge Hold Time CS Rising Edge to SCLK Edge Hold Time
t210
t512, 13 t6 t7 Write Operation t8 t9 t10 t11
8 9
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 2 and Figure 3. These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 11 SCLK active edge is falling edge of SCLK. 12 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
10 13
RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.
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AD7794
Preliminary Technical Data
+1.6 V 50 pF
Figure 1. Load Circuit for Timing Characterization
CS (I)
t1
DOUT/RDY (O) MSB LSB
t6 t5
t2 t3
SCLK (I)
t7
t4
I = INPUT, O = OUTPUT
04227-0-003
Figure 2. Read Cycle Timing Diagram
CS (I)
t8
SCLK (I)
t11
t9 t10
DIN (I) MSB LSB
04227-0-004
I = INPUT, O = OUTPUT
Figure 3. Write Cycle Timing Diagram
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 3. (TA= 25C, unless otherwise noted.)
Parameter AVDD to GND DVDD to GND Analog Input Voltage to GND Reference Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND AIN/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature TSSOP JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +7 V -0.3 V to +7 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V toA VDD + 0.3 V 10 mA -40C to +105C -65C to +150C 150C 97.9C/W 14C/W 215C 220C
AD7794
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD7794 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCLK CLK CS NC AIN6(+)/P1 AIN6(-)/P2 AIN1(+) AIN1(-) AIN2(+) AIN2(-) AIN3(+) AIN3(-)
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20
Preliminary Technical Data
DIN DOUT/RDY DVDD AVDD GND PSW AIN4(-)/REFIN2(-) AIN4(+)/REFIN2(+) AIN5(-)/IOUT1 AIN5(+)/IOUT2 REFIN1(-) REFIN1(+)
AD7794
TOP VIEW (Not To Scale)
19 18 17 16 15 14 13
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 Mnemonic SCLK Function Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can be disabled and the ADC can be driven by an external clock. This allows several ADCs to be driven from a common clock, allowing simultaneous conversions to be performed. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. No Connect Analog Input/Digital Output pin. AIN6(+) is the positive terminal of the differential analog input pair AIN6(+)/AIN6(-). Alternatively, this pin can function as a general purpose output bit referenced between AVDD and GND Analog Input/ Digital Output pin. AIN6(-) is the negative terminal of the differential analog input pair AIN6(+)/AIN6(-). Alternatively, this pin can function as a general purpose output bit referenced between AVDD and GND Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(-). Analog Input. AIN1(-) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(-). Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(-). Analog Input. AIN2(-) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(-). Analog Input. AIN3(+) is the positive terminal of the differential analog input pair AIN3(+)/AIN3(-). Analog Input. AIN3(-) is the negative terminal of the differential analog input pair AIN3(+)/AIN3(-). Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(-). REFIN1(+) can lie anywhere between VDD and GND + 0.1 V. The nominal reference voltage (REFIN1(+) - REFIN1(-)) is 2.5 V, but the part functions with a reference from 0.1 V to AVDD. Negative Reference Input. This reference input can lie anywhere between GND and AVDD - 0.1 V. Analog Input/Output of Internal Excitation Current Source. AIN5(+) is the positive terminal of the differential analog input pair AIN5(+)/AIN5(-). Alternatively, the internal excitation current source can be made available at this pin. The excitation current source is programmable so that the current can be 10 uA, 200 uA or 1 mA. Either IEXC1 or IEXC2 can be switched to this output Analog Input/Output of Internal Excitation Current Source.
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2
CLK
3
CS
4 5
NC AIN6(+)/P1
6
AIN6(-)/P2
7 8 9 10 11 12 13
AIN1(+) AIN1(-) AIN2(+) AIN2(-) AIN3(+) AIN3(-) REFIN1(+)
14 15
REFIN1(-) AIN5(+)/IOUT2
16
AIN5(-)/IOUT1
Preliminary Technical Data
Pin No. Mnemonic
AD7794
17
AIN4(+)/REFIN2(+)
18
AIN4(-)/REFIN2(-)
19 20 21 22 23
PSW GND AVDD D VDD DOUT/RDY
24
DIN
Function AIN5(-) is the negative terminal of the differential analog input pair AIN5(+)/AIN5(-). Alternatively, the internal excitation current source can be made available at this pin. The excitation current source is programmable so that the current can be 10 uA, 200 uA or 1 mA. Either IEXC1 or IEXC2 can be switched to this output. Analog Input/Positive Reference Input. AIN4(+) is the positive terminal of the differential analog input pair AIN4(+)/AIN4(-). This pin can aso function as a reference input. REFIN2(+) can lie anywhere between AVDD and GND + 0.1 V. The nominal reference voltage (REFIN2(+) - REFIN2(-)) is 2.5 V, but the part functions with a reference from 0.1 V to AVDD. Analog Input/Negative Reference Input. AIN4(-) is the negative terminal of the differential analog input pair AIN4(+)/AIN4(-). This pin also functions as the negative reference input for REFIN2. This reference input can lie anywhere between GND and AVDD - 0.1 V. Low Side Power Switch to GND. Ground Reference Point. Supply Voltage, 2.7 V to 5.25 V. Serial Interface Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, the serial interface can be operated at 3 V with AVDD at 5 V or vice versa. Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose . It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin will go high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word informa-tion is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY pin is three-stated but the RDY bit remains active. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers within the ADC, the register selection bits of the communications register identifying the appropriate register.
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AD7794 TYPICAL PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
Figure 5.
Figure 8.
Figure 6.
Figure 9.
Figure 7.
Figure 10.
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Preliminary Technical Data ON-CHIP REGISTERS
AD7794
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
CR7 WEN(0) CR6 R/W(0) CR5 RS2(0) CR4 RS1(0) CR3 RS0(0) CR2 CREAD(0) CR1 0(0) CR0 0(0)
Table 5. Communications Register Bit Designations
Bit Location CR7 Bit Name WEN Description Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the communications register. A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this position indicates that the next operation will be a read from the designated register. Register Address Bits. These address bits are used to select which of the ADC's registers are being selected during this serial interface communication. See Table 6. Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read, i.e., the contents of the data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The communications register does not have to be written to for data reads. To enable continuous read mode, the instruction 01011100 must be written to the communications register. To exit the continuous read mode, the instruction 01011000 must be written to the communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. These bits must be programmed to logic 0 for correct operation.
CR6 CR5-CR3 CR2
R/W RS2-RS0 CREAD
CR1-CR0
0
Table 6. Register Selection
RS2 0 0 0 0 0 1 1 1 1 RS1 0 0 0 1 1 0 0 1 1 RS0 0 0 1 0 1 0 1 0 1 Register Communications Register during a Write Operation Status Register during a Read Operation Mode Register Configuration Register Data Register ID Register IO Register Offset Register Full-ScaleRegister Register Size 8-Bit 8-Bit 16-Bit 16-Bit 24-Bit 8-Bit 8-Bit 24-Bit 24-Bit
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AD7794
STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; POWER-ON/RESET = 0x88)
Preliminary Technical Data
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load bits RS2, RS1 and RS0 with 0. Table 7 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
SR7 RDY(1) SR6 ERR(0) SR5 NOREF(0) SR4 0(0) SR3 1(1) SR2 CH2(0) SR1 CH1(0) SR0 CH0(0)
Table 7. Status Register Bit Designations
Bit Location SR7 Bit Name RDY Description Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange or the absence of a reference voltage. Cleared by a write operation to start a conversion. No External Reference Bit. Set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all ones. Cleared to indicate that a valid reference is applied to the selected reference pins. The NOXREF bit is enabled by setting the REF_DET bit in the Configuration register to 1. The ERR bit is also set if the voltage applied to the selected reference input is invalid. This bit is automatically cleared. This bit is automatically set. These bits indicate which channel is being converted by the ADC.
SR6
ERR
SR5
NOREF
SR4 SR3 SR2-SR0
0 1 CH2-CH0
MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; POWER-ON/RESET = 0x000A)
The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the update rate and the clock source. Table 8 outlines the bit designations for the mode register. MR0 through MR15 indicate the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit.
MR15 MD2(0) MR7 CLK1(0) MR14 MD1(0) MR6 CLK0(0) MR13 MD0(0) MR5 0(0) MR12 PSW(0) MR4 CHOP-DIS (0) MR11 0(0) MR3 FS3(1) MR10 0(0) MR2 FS2(0) MR9 0(0) MR1 FS1(1) MR8 0(0) MR0 FS0(0)
Table 8. Mode Register Bit Designations
Bit Location MR15-MR13 MR12 Bit Name MD2-MD0 PSW Description
Mode Select Bits. These bits select the operational mode of the AD7794 (See
Table 9). Power Switch Control Bit. Set by user to close the power switch PSW to GND. The power switch can sink up to 20 mA. Cleared by user to open the power switch. When the ADC is placed in power-down mode, the power switch is opened. These bits must be programmed with a Logic 0 for correct operation. These bits are used to select the clock source for the AD7794. Either the on-chip 64 kHz clock can be used or an external clock can be used. The ability to use an external clock is useful as it allows several AD7794 devices to be synchronised. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7794.
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MR11-MR8 MR7-MR6
0 CLK1-CLK0
Preliminary Technical Data
Bit Location Bit Name Description CLK1 CLK0 0 0 0 1 1 0 1 1
AD7794
MR5 MR4 MR3-MR0
0 CHOP-DIS FS3-FS0
ADC Clock Source Internal 64 kHz Clock, Internal Clock is not available at the CLK pin Internal 64 kHz Clock. This clock is made available at the CLK pin External 64 kHz Clock used. The external clock can have a 45:55 duty cycle. External Clock used. This external clock is divided by 2 within the AD7794. This allows the user to supply a clock which has a duty cycle worse than a 45:55 duty cycle to the AD7794, for example, a 128 kHz clock. This bit must be programmed with a Logic 0 for correct operation. This bit is used to enable or disable chopping. On power-up or following a reset, CHOP-DIS is cleared so chopping is enabled. When CHOP-DIS is set, chopping is disabled. Filter Update Rate Select Bits (see Table 10).
Table 9. Operating Modes
MD2 0 MD1 0 MD0 0 Mode Continuous Conversion Mode (Default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on, the first conversion is available after a period 2/ fADC when chopping is enabled or 1/ fADC when chopping is disabled. Subsequent conversions are available at a frequency of fADC with chopping either enabled or disabled, Single Conversion Mode. In single conversion mode, the ADC is placed in power-down mode when conversions are not being performed. When single conversion mode is selected, the ADC powers up and performs a single conversion, which occurs after a period 2/fADC when chopping is enabled or 1/ fADC when chopping is disabled. The conversion result in placed in the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed. Idle Mode. In Idle Mode, the ADC Filter and Modulator are held in a reset state although the modulator clocks are still provided Power-Down Mode. In power down mode, all the AD7794 circuitry is powered down including the current sources, power switch, burnout currents, bias voltage generator and CLKOUT circuitry. Internal Zero-Scale Calibration. An internal short is automatically connected to the enabled channel. A calibration takes 2 conversion cycles to complete when chopping is enabled and 1 conversion cycle when chopping is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel Internal Full-Scale Calibration. The fullscale input voltage is automatically connected to the selected analog input for this calibration. The full-scale error of the AD7794 is calbrated at a gain of 1 using the internal reference in the factory. When a channel is operated with a gain of 1 and the internal reference is selected, this factory-calibrated value is loaded into the full-scale register when a full-scale calibration is initiated. When an external reference is selected at a gain of 1, an internal fullscale calibration can be performed. When the gain equals 1, a calibration takes 2 conversion cycles to complete when chopping is enabled and 1 conversion cycle when chopping is disabled. For higher gains, 4 conversion cycles are required to perform the fullscale calibration when chopping is enabled and 2 conversion cycles when chopping is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured fullscale coefficient is placed in the fullscale register of the selected channel. Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system full-scale calibration can be performed.
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0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
AD7794
1 1 0
Preliminary Technical Data
A fullscale calibration is required each time the gain of a channel is changed. System Offset Calibration. User should connect the system zero-scale input to the .channel input pins as selected by the CH2-CH0 bits. A system offset calibration takes 2 conversion cycles to complete when chopping is enabled and one conversion cycle when chopping is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. System Full-Scale Calibration. User should connect the system full-scale input to the .channel input pins as selected by the CH2-CH0 bits. A calibration takes 2 conversion cycles to complete when chopping is enabled and one conversion cycle when chopping is disabled.. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured fullscale coefficient is placed in the fullscale register of the selected channel. A fullscale calibration is required each time the gain of a channel is changed.
1
1
1
Table 10. Update Rates Available (Chopping Enabled)
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fADC (Hz) x 500 250 125 62.5 50 41.6 33.3 19.6 16.6 16.6 12.5 10 8.33 6.25 4.17 Tsettle (ms) x 5 8 16 32 40 48 60 101 120 120 160 200 240 320 480 Rejection@ 50 Hz / 60 Hz (Internal Clock)
90 dB (60 Hz only) 84 dB (50 Hz only) 70 dB (50 Hz and 60 Hz) 67 dB (50 Hz and 60 Hz) 69 dB (50 Hz and 60 Hz) 73 dB (50 Hz and 60 Hz) 74 dB (50 Hz and 60 Hz) 79 dB (50 Hz and 60 Hz)
With chopping disabled, the update rates remain unchanged but the settling time for each update rate is reduced by a factor of 2. The rejection at 50 Hz/60 Hz for a 16.6 Hz update rate degrades to 60 dB.
CONFIGURATION REGISTER (RS2, RS1, RS0 = 0, 1, 0; POWER-ON/RESET = 0x0710)
The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain and select the analog input channel. Table 11 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit locations, CON denoting the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
CON15 VBIAS1(0) CON7 REFSEL1(0) CON14 VBIAS0(0) CON6 REFSEL0(0) CON13 BO(0) CON5 REF_DET(0) CON12 U/B (0) CON4 BUF(1) CON11 0(0) CON3 CH3(0) CON10 G2(1) CON2 CH2(0) CON9 G1(1) CON1 CH1(0) CON8 G0(1) CON0 CH0(0)
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Preliminary Technical Data
Table 11. Configuration Register Bit Designations
Bit Location CON15- CON14 Bit Name 0
AD7794
CON13
BO
CON12
U/B
CON11 CON10CON8
0 G2-G0
Description Bias Voltage Generator Enable. The negative terminal of the analog inputs can b e biased up to VDD/2. VBIAS1 VBIAS0 Bias Voltage 0 0 Bias Voltage Generator Disabled 0 1 Bias Voltage Generator connected to AIN1(-) 1 0 Bias Voltage Generator connected to AIN2(-) 1 1 Bias Voltage Generator connected to AIN3(-) This bit must be programmed with a Logic 0 for correct operation. Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer or in-amp is active. Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 0x000000 output and a full-scale differential input will result in 0xFFFFFF output. Cleared by the user to enable bipolar coding. Negative full-scale differential input will result in an output code of 0x000000, zero differential input will result in an output code of 0x800000, and a positive full-scale differential input will result in an output code of 0xFFFFFF. This bit must be programmed with a Logic 0 for correct operation. Gain Select Bits. Written by the user to select the ADC input range as follows G2 G1 G0 Gain ADC Input Range (2.5V Reference) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 (In-Amp not used) 2 (In-Amp not used) 4 8 16 32 64 128 2.5 V 1.25 V 625 mV 312.5 mV 156.2 mV 78.125 mV 39.06 mV 19.53 mV
CON7CON6
REFSEL1/REFSEL0
Reference Select Bits. The reference source for the ADC is selected using these bits. REFSEL1 REFSEL0 Reference Source 0 0 External Reference applied between REFIN1(+) and REFIN1(-) 0 1 External Reference applied between REFIN2(+) and REFIN2(-) 1 0 Internal 1.17 V Reference 1 1 Reserved Enables the Reference Detect Function. When set, the NOXREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.5 V. When cleared, the reference detect function is disabled. Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. For gains of 1 and 2, the buffer can be enabled or disabled. For higher gains, the buffer is automatically enabled. Channel Select bits. Written by the user to select the active analog input channel to the ADC. CH3 CH2 CH1 CH0 Channel Calibration Pair 0 0 0 0 AIN1(+) - AIN1(-) 0 0 0 0 1 AIN2(+) - AIN2(-) 1 0 0 1 0 AIN3(+) - AIN3(-) 2 0 0 1 1 AIN4(+) - AIN4(-) 3
CON5
REF_DET
CON4
BUF
CON3CON0
CH3-CH0
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AD7794
Bit Location Bit Name Description 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1
Preliminary Technical Data
0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1
AIN5(+) - AIN5(-) AIN6(+) - AIN6(-) Temp Sensor VDD Monitor AIN1(-) - AIN1(-) Reserved Reserved Reserved Reserved Reserved Reserved Reserved
3 3 Automatically selects the internal reference and sets the gain to 1 Automatically selects the internal 1.17 V reference and sets the gain to 1/6 0
DATA REGISTER (RS2, RS1, RS0 = 0, 1, 1; POWER-ON/RESET = 0x000000)
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set.
ID REGISTER (RS2, RS1, RS0 = 1, 0, 0; POWER-ON/RESET = 0xXF)
The Identification Number for the AD7794 is stored in the ID register. This is a read-only register.
IO REGISTER (RS2, RS1, RS0 = 1, 0, 1; POWER-ON/RESET = 0x00)
The I/O register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the excitation currents and select the value of the excitation currents. Table 12 outlines the bit designations for the IO register. IO0 through IO7 indicate the bit locations, IO denoting the bits are in the IO register. IO7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
IO7 0(0) IO6 IOEN(0) IO5 IO2DAT(0) IO4 IO1DAT(0) IO3 IEXCDIR1(0) IO2 IEXCDIR0(0) IO1 IEXCEN1(0) IO0 IEXCEN0(0)
Table 12 Filter Register Bit Designations
Bit Location IO7 IO6 Bit Name 0 IOEN Description This bit must be programmed with a Logic 0 for correct operation. Configures the pins AIN6(+)/P2 and AIN6(-)/P2 are analog input pins or digital output pins. When this bit is set, the pins are configured as digital output pins P1 and P2. When this bit is cleared, these pins are configured as analog input pins AIN6(+) and AIN6(-). P2/P1 Data. When IOEN is set, the data for the digital output pins P1 and P2 is written to bits IO2DAT and IO1DAT. Direction of Current Sources Select bits. IEXCDIR1 IEXCDIR0 Current Source Direction 0 0 Current Source IEXC1 connected to pin IOUT1, Current Source IEXC2 connected to pin IOUT2 0 1 Current Source IEXC1 connected to pin IOUT2, Current Source IEXC2 connected to pin IOUT1 1 0 Both Current Sources connected to pin IOUT1. Permitted only when the current sources are set to 10 uA or 200 uA 1 1 Both Current Sources connected to pin IOUT2. Permitted only when the current sources are set to 10 uA or 200 uA These bits are used to enable and disable the current sources along with selecting the value of the
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IO5-IO4 IO3-IO2
IO2DAT/IO1DAT IEXCDIR1- IEXCDIR0
IO3-IO2
IEXCEN1-
Preliminary Technical Data
Bit Location Bit Name IEXCEN0 Description excitation currents. IEXCEN1 IEXCEN0 0 0 0 1 1 0 1 1
AD7794
Current Source Value Excitation Currents Disabled 10 uA 200 uA 1 mA
PR04854-0-6/04(PrE)
OFFSET REGISTER (RS2, RS1, RS0 = 1, 1, 0; POWER-ON/RESET = 0x800000)
The offset register holds the offset calibration coefficient for the ADC. The power-on-reset value of the internal zero-scale calibration coefficient register is 800000 hex. The AD7794 has 4 offset registers. Channels AIN1 to AIN3 have dedicated offset registers while channels AIN4, AIN5 and AIN6 share an offset register. Each of these registers is a 24-bit read/write register. This register is used in conjunction with its associated full-scale register to form a register pair. The power-on-reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7794 must be placed in power down mode or idle mode when writing to the offset register.
FULL-SCALE REGISTER (RS2, RS1, RS0 = 1, 1, 1; POWER-ON/RESET = 0x5XXXX5)
The full-scale registers is a 24-bit register that holds the full-scale calibration coefficient for the ADC. The AD77794 has 4 full-scale registers. Channels AIN1, AIN2 and AIN3 have dedicated full-scale registers while channels AIN4, AIN5 and AIN6 share a register. The full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power down mode or idle mode. These registers are configured on power-on with factory-calibrated internal full-scale calibration coefficients, the factory calibration being performed with the gain set to 1 and using the internal reference. Therefore, every device will have different default coefficients. These default values are used when the device is operated with a gain of 1 and when the internal reference is selected. For other gains or when the external reference is used at a gain of 1, these default coefficients will be automatically overwritten if an internal or system full-scale calibration is initiated by the user. A full-scale calibration should be performed when the gain is changed.
TYPICAL APPLICATION (FLOWMETER)
VDD
IN+ OUTIN+ OUTINOUT+ INOUT+
REFIN1(+) AIN1(+) AIN1(-)
GND
AVDD VDD
AIN2(+) AIN2(-) AIN3(+)
IN-AMP MUX
SIGMA DELTA ADC
SERIAL INTERFACE AND CONTROL LOGIC
DOUT/RDY DIN SCLK CS
AIN3(-) RCM IOUT1 REFIN1(-) PSW GND
GND VDD
INTERNAL CLOCK
DVDD
AD7794
CLK
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